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Digital Hardware Testing: Transistor-Level Fault, Modeling and Testing

Digital Hardware Testing: Transistor-Level Fault, Modeling and Testing

By (author): Rochit Rajsuman
Copyright: 1992
Pages: 371
ISBN: 9780890065808

Artech House is pleased to offer you this title in a special In-Print-Forever® ( IPF® ) hardbound edition. This book is not available from inventory but can be printed at your request and delivered within 2-4 weeks of receipt of order. Please note that because IPF® books are printed on demand, returns cannot be accepted.

Print Book £102.00 Qty:
Digital Hardware Testing presents realistic transistor-level fault models and testing methods for all types of circuits. The discussion details design-for-testability and built-in self-test methods, with coverage of boundary scan and emerging technologies such as partial scan, cross check, and circular self-test-path.
Faults in Digital Circuits. Bridging Faults in Random Logic. Open Circuit Faults in Random Logic. Fault Simulation and Test Generation. Testing of Structured Designs (PLAs). Memory Testing. Testing of Sequential Circuits. Microprocessor Testing. Design for Testability. Current Testing. Special Test Methods.
  • Rochit Rajsuman Rochit Rajsuman manages test research at Advantest America R & D Center in Santa Clara, California. He received his B.Tech. in Electrical Engineering from K.N. Institute of Technology, India, his M.S. in Electrical Engineering from the University of Oklahoma, and his Ph.D. in Electrical Engineering from Colorado State University. He is a senior member of the IEEE and a Golden Core member of the Computer Society.
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