LinkedIn Facebook twitter home page

Advanced Search

Change Location

 
Artech House UK
Layout Techniques for Integrated Circuit Designers

Layout Techniques for Integrated Circuit Designers

By (author): Mikael Sahrling
Copyright: 2022
Pages: 463
ISBN: 9781630819101
Coming Soon: Available 09/30/2022
List Price: £135.00

New Release Discount Price
Print Book £101.00 Qty:
This book provides complete step-by-step guidance on the physical implementation of modern integrated circuits, showing you their limitations and guiding you through their common remedies. The book describes today’s manufacturing techniques and how they impact design rules. You will understand how to build common high frequency devices such as inductors, capacitors and T-coils, and will also learn strategies for dealing with high-speed routing both on package level and on-chip applications. Numerous algorithms implemented in Python are provided to guide you through how extraction, netlist comparison and design rule checkers can be built. The book also helps you unravel complexities that effect circuit design, including signal integrity, matching, IR drop, parasitic impedance and more, saving you time in addressing these effects directly. You will also find detailed descriptions of software tools used to analyze a layout database, showing you how devices can be recognized and connectivity accurately assessed. The book removes much of fog that often hides the inner workings of layout related software tools and helps you better understand: the physics of advanced nodes, high speed techniques used in modern integrated technologies, and the inner working of software used to analyze layout databases. This is an excellent resource for circuit designers implementing a schematic in a layout database, especially those involved in deep submicron designs, as well as layout designers wishing to deepen their understanding of modern layout rules.
Semiconductor Manufacturing, Layout Preliminaries, Layout with Small Geometry CMOS technologies, Layout with Bipolar Technologies, High Speed Layout Flow, Extraction Techniques, Netlist Comparators, Design Rule Checkers
  • Mikael Sahrling

    is a Principal Electronics Engineer working on developing high speed electrical interfaces for the Test & Measurement and communication industries. He has over 25 years of experience developing integrated circuits and many of the projects he has been a part of has brought in 10-100 millions of dollars in revenue. Mikael has worked for many of the leading analog chip companies like Semtech Corporation, Maxim Integrated, and Tektronix Inc. He is presently employed by IPG Photonics where he is the lead Analog Design Engineer. His special interest is in high speed active and passive design with a bandwidth of several tens of GigaHertz.

Newsletter Signup

Permissions