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System-on-a-Chip: Design and Test

System-on-a-Chip: Design and Test

By (author): Rochit Rajsuman
Copyright: 2000
Pages: 294
ISBN: 9781580531078

Print Book £94.00 Qty:
eBook £71.00
Starting with a basic overview of system-on-a-chip (SoC), including definitions of related terms, this new book helps you understand SoC design challenges, and the latest design and test methodologies. You see how ASIC technology evolved to an embedded cores-based concept that includes pre-designed, reusable Intellectual Property (IP) cores that act as microprocessors, data storage devices, DSP, bus control, and interfaces - all stitched together by a User 's Defined Logic (UDL). Part One features a discussion of SoC-related design difficulties including hardware-software co-design, reuse design, and cores design. You get practical, real-world design guidance referencing actual product specifications, delivery requirements, and system integration requirements in use by commercial enterprises and under evaluation by the SoC community. Significant attention is paid to the rules and guidelines for making SoC design reusable, including RTL coding guidelines and design validation. Part One concludes with the information you need to develop test benches at both the cores and SoC level. Part Two contains a review of the challenges you face in testing SoC and test methodologies for overcoming these hurdles. Test methods for embedded logic cores, microprocessor cores, micro-controller cores and large memory blocks are included, as well as methods for testing embedded analog and mixed-signal circuits, and Iddq testing on SoC. You also get an overview of material handling, speed-binning, and production flow to apply your knowledge to actual production processes. System-on-a-Chip: Design and Test is an excellent, one-stop reference for SoC and ASIC design engineers, IP designers and providers, and test engineers seeking comprehensive information on SoC design, testing, and production.
Part One - Design.Introduction. Design Methodology for SoC Logic Cores. RTL Guidelines for Design Reuse. Verification. Design Validation. Design Examples. Part Two - Test.Introduction to SoC Testing of Logic Cores. Testing of Embedded Memories. Testing of Analog and Mixed-Signal Circuits. IDDQ Testing. Production Testing. Summary and Conclusion.
  • Rochit Rajsuman Rochit Rajsuman manages test research at Advantest America R & D Center in Santa Clara, California. He received his B.Tech. in Electrical Engineering from K.N. Institute of Technology, India, his M.S. in Electrical Engineering from the University of Oklahoma, and his Ph.D. in Electrical Engineering from Colorado State University. He is a senior member of the IEEE and a Golden Core member of the Computer Society.
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